As devices achieve smaller and smaller geometries, electric fields across the oxide layer and between drain and source can become larger. As these electric fields are increased there is correspondingly an increased probability that several harmful effects are induced. These harmful effects include impact ionization, hot carrier interface damage, and hot carrier injection (HCI) into the oxide. As interface damage and/or charge trapping occurs in the oxide, performance of the semi-conductor device may be degraded to the point of failure or to the point at which the risk of failure is large.
Conventionally, characterizing the impact of hot carrier injection requires measuring a set of baseline parameters, such as, but not limited to, drain-source voltage (Vds), substrate current (Isub), etc. A series of stress cycles at different stress levels (i.e., elevated Vds or Isub states) are used to accentuate the hot carrier injection problem. The device parameters are tracked and measured after each stress cycle, thereby providing some indication of the cumulative degradation resulting from the stress test. Prediction of real device performance under normal operating or use conditions can be extrapolated from the results of the stress test.
The phenomenon of punchthrough voltage reduction due to hot-carrier injection of charged particles into the gate oxide of IGFETs is known in the art (see, e.g., U.S. Pat. No. 5,606,518). The phenomenon occurs during post-manufacture use. When a field effect transistor (FET) is held in a turned-on state (conductive state), charge carriers move through a channel region of the transistor from the source region to the drain region. The moving charge carriers gain energy as they come closer to the drain region. Some of the highly-energized charge carriers that are approaching the drain region collide with nuclei of the channel region and generate electron-hole pairs or other ionized anomalies. Due to the distribution of electric fields near the drain, the electron and hole of each collision-induced electron-hole pair tend to separate from one another and preferentially migrate towards or away from the gate of the device. Some of the migrating charge-particles become trapped in the gate insulating layer that separates the gate from the channel or at the interface of the gate insulating layer and the channel.
When a turn-off voltage is later applied to the gate of the same transistor for the purpose of switching the transistor into an off state, it is expected that no current will flow through the device. However, the charged particles which have collected over time and become trapped at the channel/gate-insulator interface, or within the gate insulating layer, reduce the effective channel length. This in turn reduces the punchthrough voltage (Vpt) of the device. Operation at or above the punchthrough level induces an undesirable flow of leakage current between the source and drain. Such leakage current, when it occurs due to operation at or slightly above Vpt, is typically on the order of one or less microampere (xe2x89xa61 xcexcA) per transistor and is rarely thought to be of consequence when one considers a circuit having only a few transistors.
However, modern integrated circuit designs usually call for the inclusion of millions of transistors on a single monolithic substrate. A leakage current of just one nanoampere (nA) per transistor translates into a larger scale leakage current of one or more milliamperes (mA) per integrated circuit (IC) chip in high-density designs that include millions of transistors per IC chip. This magnitude of leakage is generally unacceptable in low-power environments. It is particularly unacceptable when the IC chip is one of many similarly leaking devices, all residing in a system that is supposed to have very low power consumption.
An example of such a power-frugal system is a portable xe2x80x9cnotebookxe2x80x9d or xe2x80x9chandheldxe2x80x9d computer that is to be powered by a battery of limited amp/hours. It is common to require such a computer to have one or more power-conserving standby modes in which the power consumption of inactive computing resources is minimized by putting them to xe2x80x9csleepxe2x80x9d. This helps to extend the operating time of the computer after each battery charge.
System lifetimes (that is, time prior to a predetermined amount of device degradation has occurred) are typically specified as being at least 1 year to 3 years in order to satisfy consumer warranty requirements, and more often as being at least 5 to 10 years, to satisfy market requirements. The required lifetime of a given system can, of course, be much longer. It is often required, or at least desirable, to keep the power consumption of circuits that are in low-power standby mode below a specified maximum during the specified lifetime of the system.
Conventional hot carrier reliability methods can only characterize the median (xcfx8450) case. Accordingly, only the nominal hot-carrier injection (HCI) lifetime may be determined without counting any critical dimension variation or mechanical stress induced channel stress variations. Therefore, conventional methods may be expected to give higher lifetimes than is necessary. However, different devices and different technologies display some corner-to-corner variation in terms of the substrate current (Isub) as well as the drain saturation current (Idsat). Accordingly, it would be advantageous to choose the lifetime satisfied by 99.9% of devices (xcfx840.1) (or other suitable lifetime level) for a much safer lifetime projection rather than a simple median (xcfx8450) case because the current simple median (xcfx8450) case cannot account for any Isub/Idsat variation due to extrinsic factors.
Accordingly, there is a need for a semiconductor device qualification method for providing an improved projected lifetime for fabricated devices. There is also a need for a method of projecting the lifetime of semiconductor devices which improves lifetime projections over conventional methods by considering corner-to-corner variation of currents in the device. Further, there is a need for a method of qualifying metal oxide semiconductor (MOS) devices which may be degraded by hot carrier injection effects.
It would be desirable to provide a system and/or method that provides one or more of these or other advantageous features. Other features and advantages will be made apparent from the present specification. The teachings disclosed extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
An exemplary embodiment relates to a method of generating a lifetime projection for semiconductor devices. The method includes collecting device lifetime information for a plurality of semiconductor devices at more than one stress condition. The stress condition is at least a substrate current stress condition. The method also includes calculating, for each stress condition, a lifetime level at which a predetermined percentage of devices will exceed. Each lifetime level is a data point on the stress condition versus lifetime graph. Further, the method of generating a lifetime projection for semiconductor devices includes calculating the slope of an interpolated line through the data point for each stress condition versus lifetime graph. Further still, the method includes determining a line corresponding to a ratio of substrate current to gate current versus drain voltage relationship that satisfies the lifetime level, based on the interpolated line information.
Another exemplary embodiment relates to a method of generating a lifetime projection for semiconductor devices. The method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes determining information for semiconductor devices in a first mode. Further still, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed. Further still, the method includes extrapolating the lifetime for devices used at operating conditions.
Yet another exemplary embodiment relates to a method of qualifying semiconductor devices based on projected lifetime. The method includes establishing a maximum relationship between a ratio of substrate current to gate current and drain voltage. The method also includes subjecting a semiconductor device to an operating condition. Further, the method includes determining the ratio for the semiconductor device and comparing the ratio to the maximum relationship.
Yet still another exemplary embodiment relates to a method of generating a lifetime projection for semiconductor devices. The method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining that the lifetime information at a stress condition approximates a bimodal distribution, having a first and a second mode. Further, the method includes determining information for semiconductor devices in the first mode. Further still, the method includes calculating a lifetime at each stress condition based on information related to the first mode. Further still, the method includes extrapolating the lifetime for devices used at operating conditions.
Alternative exemplary embodiments relate to other features and combination of features as may be generally recited in the claims.